1. Field of the Invention
The present invention relates to a memory testing apparatus and testing method in which the test results corresponding to the performance of a memory under test are stored in a failure memory and subsequently counting the failure bits stored in the failure memory, and more particularly, to a memory testing apparatus and method, which can reduce the time required for functional testing of memory devices.
2. Description of the Related Art
Memory testing apparatuses perform tests for various operational parameters of a memory, such as a power supply voltage margin and access time, and count defective bits of the memory. A conventional memory testing apparatus, such as the one disclosed in Japanese Laid-Open Patent Publication No. hei 9-33615, determines whether a memory is eligible to undergo subsequent wafer processing operations based on the number of defective bits detected in the memory. If the number of defective bits detected in the memory exceeds a predetermined number, the memory is determined to be irreparable and is then excluded from subsequent wafer processing operations. If, on the other hand, the memory is determined to be repairable, the memory will be subjected to additional processing during which an attempt to repair the memory will be included. A conventional memory testing apparatus will now be described more fully with reference to FIG. 1.
FIG. 1 is a block diagram of according to one example of a conventional memory testing apparatus. As illustrated in FIG. 1, a test head 1 is electrically connected to a memory 10 to be tested (hereinafter, referred to as a device under test (DUT)) for transmitting/receiving signals to/from the DUT 10. The test head 1 includes a format controller FC, a driver D, a comparator C, and a digital comparator DC. The format controller FC reshapes a pattern input thereto and outputs the reshaped pattern to the driver D. The driver D receives the reshaped pattern from the format controller FC and adjusts or sets the desired voltage level, and outputs the adjusted pattern to the DUT 10. The comparator C receives the output from the DUT 10 and checks the voltage level of the output signal. The digital comparator DC compares outputs received by the comparator C with expected pattern data received from the pattern generator to determine whether the DUT 10 fails or passes the memory test.
A pattern generator 2 outputs patterns (i.e., an input pattern and an expected output pattern) to the test head 1 and simultaneously generates addresses. An address pointer 3 may also be used for generating addresses. A multiplexer 4 selects between the addresses generated by the pattern generator 2 or the addresses generated by the address pointer 3. A failure memory 5 stores failure data obtained from the test head 1 corresponding to the addresses received from the multiplexer 4. A failure bit counter 6 counts the failure bits of the failure memory 5. A controller 7 controls the address pointer 3, the multiplexer 4, the failure memory 5, and the failure bit counter 6. A central processing unit (CPU) 8 controls the pattern generator 2 and the controller 7.
The operation of the conventional testing apparatus generally according to FIG. 1 will now be described further with reference to the operational flowchart for such a conventional testing apparatus provided in FIG. 2. As illustrated in FIG. 2, the CPU 8 sets the level of a power supply voltage to be supplied to the DUT 10 to a predetermined level, such as 3.3 V, in step S11. In response to this voltage setting, the test head 1 will apply the predetermined voltage to the power port(s) of the DUT 10 using a direct current (DC) generator (not shown).
The CPU 8 will then instruct the pattern generator 2 to initiate a function test using a signal A′ in step S12. The CPU 8 also informs the controller 7 that the pattern generator 2 has been instructed to initiate the function test. In response, the controller 7 will set the multiplexer 4 to select the addresses generated by the pattern generator 2 and also command the failure memory 5 to perform a write operation.
The pattern generator 2 outputs a background pattern (sometimes also referred to as a rear or initialization pattern) that will write a data value of “1” or “0” into each cell of the memory in order to initialize the individual memory cells with a predetermined state. The format controller FC receives the background pattern from the pattern generator 2, reshapes the background pattern, outputs the reshaped background pattern to the DUT 10 via a driver D, and performs a write operation in step S13.
Once the memory cells have been initialized, during step S14 the pattern generator 2 will generate and output a read/write test pattern and corresponding memory addresses to the format controller FC. The format controller FC will reshape the addresses and the test pattern and output the reshaped addresses and the reshaped input pattern to the DUT 10 via the driver D. The digital comparator DC will receive the resulting output pattern from the DUT 10 via the comparator C and compare the output pattern from the DUT 10 with the expected output pattern received from the pattern generator 2. Based on this comparison, the digital comparator DC will determine whether the DUT 10 has passed or failed the function test and will output failure data as the determination result. The failure data output from the digital comparator DC will be associated within the failure memory 5 to the corresponding address data received from the multiplexer 4. The failure memory 5 typically maintains a once-failed state whereby a memory cell address that has failed to respond correctly to any test pattern will be recorded as a “failed” cell even if it passes other test patterns. In step S15, the pattern generator 2 notifies the CPU 8 that the function test has been completed by using a signal B′.
In step S16, the CPU 8 commands the controller 7 to count the failure bits of the DUT 10. The controller 7 sets the multiplexer 4 to output the address information from the address pointer 3 and commands the failure memory 5 to read the failure data. In step S17, the address pointer 3 sequentially outputs the address of each cell of the failure memory 5 using the multiplexer 4, and the failure bit counter 6 counts the number of failure bits of the failure memory 5. In step S18, the controller 7 notifies the CPU 8 that the counting of the failure bits of the failure memory 5 has been completed in response to an ending signal output from the address pointer 3.
Thereafter, the CPU 8 determines if each of the power supply voltage tests has been completed. If additional supply voltage tests are required, the operation returns to step S11 where the CPU 8 resets the level of the power supply voltage to the next scheduled voltage that will be supplied to the DUT 10 by test head 1. The remaining scheduled voltages may be higher, such as 3.6 V, or lower, such as 3.0 V, than the initial power supply voltage as operational margin tests to aid in the detection of “soft” cell errors. Once the power supply voltage has been reset, steps S12–S18 are performed to complete another functional test cycle on the DUT 10. This sequence of resetting the power supply voltage and rerunning the functional test steps will continue until the CPU 8 determines that functional tests have been run at each of the scheduled voltages and the testing of the DUT 10 is complete.
For example, using the conventional method and apparatus to conduct a series of four functional tests, AC1–AC4 and collect the corresponding failure bit counts FB1–FB4 will involve an operation sequence of:AC1→FB1→AC2→FB2→AC3→FB3→AC4→FB4.with each of the operations requiring a certain amount of time to complete. As a result, the cumulative time required to complete the full testing and failure bit counting sequence may be represented by:TAC1+TFB1+TAC2+TFB2+TAC3+TFB3+TAC4+TFB4=Total Test Time.
As described above, in the conventional prior art, the various operational margin tests and the process of counting the defective bits of a memory device under test are performed sequentially. However, as the storage capacity of the memory devices being tested increases, the time and expense required to perform such operational margin tests on the predetermined memory and count the detected failures also increases.